1. Field of the Invention
The present invention relates to an integrated circuit containing bipolar and complementary MOS transistors on a common substrate wherein the emitter terminals of the bipolar transistors as well as the gate electrodes of the MOS transistors are composed of the same material including at least one layer of a refractory metal silicide of a metal such as tantalum, tungsten, molybdenum, titanium or platinum.
2. Description of the Prior Art
An integrated circuit containing a bipolar transistor and an MOS transistor which are generated on a chip and wherein the contacts from the metal interconnect level to the diffused regions of the bipolar transistor and the gate electrode are composed of the same material consisting of a silicide of a refractory metal is known from European Patent Application No. 0 10 1 000. By employing such a silicide, the implantation mask used in traditional methods is eliminated, and the contacting of base, emitter and collector regions becomes independent of the metallization grid.
When bipolar transistors and complementary MOS transistors are to be produced simultaneously on a chip, an n-well CMOS process is used to form the base and the emitter regions and the base terminals of the bipolar transistors are simultaneously implanted with the source and drain regions of the MOS transistors and are contacted with metal. Such a process has been described, for example, in German Patent Application No. P 35 19 790.0 (corresponding to Jacobs et al U.S. Ser. No. 869,306, filed June 2, 1986, and assigned to the assignee of the present application). In this process, npn bipolar transistors are located in n-doped wells, an n-well forming the collector of the transistor an covering buried n.sup.+ -doped regions which are connected in the bipolar transistor region by deeply extending collector terminals. The buried part and the collector terminal are generated before the well in this process. The well implantation is self-adjusting to the implantation of the deep collector terminal annularly placed into the well. A reduction of collector series resistance as well as an increased latch-up stability are achieved.
The following disadvantages, however, occur due to the process limitations, and due to the metal contacting.
(1) The transistor size is limited by the metallization grid.
(2) The distance from emitter to base contact is dependent on adjustment.
(3) Employing different dopants for generating the emitter zones of the bipolar transistor and the source/drain zones of the n-channel MOS transistors in the substrate is only possible with the use of an additional photolithography step.